# -*- mode:python -*-

# Copyright (c) 2009-2010 HIT Microelectronic Center
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gou Pengfei
#

Import('*')

Source('static_inst.cc');
Source('exetrace.cc');
SimObject('EdgeExeTracer.py')
SimObject('EdgeInstTracer.py')

if 'SimpleEdgeCPU' in env['CPU_MODELS'] or 'DistributedEdgeCPU' in env['CPU_MODELS']:
    Source('fu_pool.cc')
    Source('store_set.cc')
    
    if 'SimpleEdgeCPU' in env['CPU_MODELS']:
        Source('cpu.cc')
        Source('fetch.cc')
        Source('thread_context.cc')
        Source('base_dyn_inst.cc')
        Source('base_block.cc')
        Source('map.cc')
        Source('commit.cc')
        Source('lsq.cc')
        Source('lsq_unit.cc')
        Source('rob.cc')
        Source('bpred_unit.cc')
        Source('block.cc')
        Source('inst_queue.cc')   
        Source('execute.cc')
        Source('dyn_inst.cc')
        Source('mem_dep_unit.cc')
        Source('simple_cpu_builder.cc')
        Source('edge_sim_point.cc')

    SimObject('DerivEdgeCPU.py')

    if 'SimpleEdgeCPU' in env['CPU_MODELS']:
        SimObject('SimpleEdgeCPU.py')
    
    SimObject('FUPool.py')
    SimObject('FuncUnitConfig.py')
    
TraceFlag('EdgeFetch')
TraceFlag('EdgeCPU')
TraceFlag('EdgeReg')
TraceFlag('EdgeFetchTest')
TraceFlag('EdgeMap')
TraceFlag('EdgeBlock')
TraceFlag('EdgeExe')
TraceFlag('EdgeLSQ')
TraceFlag('EdgeLSQUnit')
TraceFlag('EdgeLSQWriteBack')
TraceFlag('EdgeIQ')
TraceFlag('EdgeCommit')
TraceFlag('EdgeCommitResult')
TraceFlag('EdgeCommitResultSym')
TraceFlag('EdgeMemDepUnit')
TraceFlag('EdgeROB')
TraceFlag('EdgeRegDep')
TraceFlag('EdgeRAS')
TraceFlag('EdgePredUnit')
TraceFlag('StoreSet')
TraceFlag('EdgeBlockOutput')
TraceFlag('EdgeBlockCount')
TraceFlag('EdgePerceptron')
TraceFlag('EdgeOPN')
TraceFlag('EdgeExeUnit')
TraceFlag('EdgeSimPoint')
TraceFlag('EdgeBlockType')

TraceFlag('EdgeIQTest')
TraceFlag('EdgeTickSeparation')

CompoundFlag('EdgePred', ['EdgeRAS', 'EdgePredUnit'])

CompoundFlag('EdgeCPUAll', ['EdgeFetch', 'EdgeCPU', 'EdgeReg', 'EdgeMap', 'EdgeBlock', 
                            'EdgeExe', 'EdgeLSQ', 'EdgeLSQUnit', 'EdgeIQ', 'EdgeCommit', 'EdgeMemDepUnit',
                            'EdgeROB', 'StoreSet', 'EdgeLSQWriteBack', 'EdgeCommitResult', 'EdgeRegDep',
                            'EdgeRAS', 'EdgePredUnit','EdgeOPN','EdgeExeUnit','EdgeTickSeparation',
                            'EdgeBlockType'])   
                                         
                                         
